It has been conventional in disk drive storage systems to use continuous time peak detection schemes to recover digital data written as a series of magnetic transitions on a recording surface of a rotating magnetic disk. Recently, sampled data detection techniques such as Partial Response ("PR") signaling and Maximum Likelihood ("ML") sequence detection (collectively "PRML") have been employed in magnetic recording systems. An example of a PRML data channel architecture is illustrated in commonly assigned U.S. Pat. No. 5,341,249 issued Aug. 23, 1994, to Abbott et al., the disclosure of which is hereby incorporated by reference in its entirety as if fully set forth herein.
Typical PRML read channels have ML detectors that determine the data based on an analysis of samples taken from an analog waveform read from a disk, for example, rather than just one peak point as is the case in known peak detection techniques. Digital sample values are typically obtained by using an analog to digital ("A/D") converter that quantizes the read waveform at predetermined proper sampling times. The sampling times are controlled by the clock to the A/D converter which must be synchronized and phase aligned to the incoming data waveform if data is to be reliably recovered.
To achieve this proper timing synchronization, PRML channels typically employ a timing loop, such as the timing loops disclosed in U.S. Pat. No. 5,341,249, and in commonly assigned, U.S. Pat. No. 5,258,933 to Johnson et al., the disclosure of which is hereby incorporated by reference in its entirety, to rapidly acquire frequency and phase synchronization of the A/D converter clock with the incoming data stream.
The timing loops in such PRML channels typically have a phase locked loop ("PLL") to generate a coherent clock so that data samples may be taken at particular places on the received analog signal. Phase and frequency of the data are detected by digitally processing the data samples rather than by comparing signal transition edges as was the case in prior peak detection techniques. The digital circuitry processes the data samples to make phase/frequency error estimates and then typically sends these digital estimates to a timing control digital to analog converter ("DAC") where they are converted into analog error estimates for timing loop processing.
The amount of time it takes for a timing loop to recover a synchronous data clock signal is important both in terms of speed of acquisition, and, in the case of disk drive recording systems, the amount of disk space that must be devoted to this purpose. In known disk drive storage systems, when READ mode is entered, the PLL typically acquires the initial data clock frequency and phase from a known preamble waveform that precedes data reception. It is important during acquisition mode for the timing loop to quickly recover timing information from the preamble so that the amount of disk area assigned to the preamble may be minimized.
In order to minimize the initial starting phase error of the sampling clock with respect to the preamble waveform, and thereby minimize acquisition time and disk space, "zero phase start" techniques have been used in conjunction with timing control loops in both peak detection and PRML systems. This technique involves causing a phase pause of controllable duration to be applied within a timing control loop, and then to attempt to restart the timing control loop in phase alignment with the incoming analog waveform.
In prior peak detection systems, a voltage controlled oscillator ("VCO") has had an ENABLE input that allows for controlled starting and stopping of the oscillator. When the ENABLE control is asserted, the oscillator begins oscillating in a known state. The clock transition rising edges, which contain the important timing aspect of the resultant clock signal, occur at a fixed delay interval after assertion of the ENABLE control signal.
The prior zero phase start logic sensed a transition of a read gate control signal ("RDGATE") from inactive to active, (indicating initiation of READ mode), and deasserted ENABLE, stopping the VCO. Upon arrival of a subsequent raw data transition edge in the analog data stream at the zero phase start logic, the ENABLE control signal was reasserted and the timing loop VCO restarted. A timing delay block took into account the delays associated with detecting the raw data edge, and restart of the VCO, so that the next raw data edge, and the first clock edge output by the timing loop VCO coincided at the input to the phase-frequency detector simultaneously, or nearly simultaneously. Thus, the starting phase error was near zero, and PLL acquisition time was reduced.
A zero phase start circuit for timing acquisition in a PRML recording channel is found in an article by Dolivo et al., entitled "Fast Timing Recovery for Partial-Response Signaling Systems", Proc. of ICC '89 (IEEE), Boston, Mass., Jun. 11-14, 1989. In that article, a solution is proposed to minimize the "hang-up" effect said to occasionally manifest itself when the starting phase for timing acquisition occurs halfway between desired sampling instances. The authors discuss exploitation of a priori knowledge regarding the structure of the preamble used for timing acquisition to create a hysteresis effect in the decisional process during timing acquisition, thereby making loop hang-up unlikely.
U.S. Pat. No. 5,341,249 and U.S. Pat. No. 5,258,933 to Johnson et al., discloses a zero phase start circuit for a PRML channel adapted to a disk drive employing zoned data recording techniques. In those patents, when timing acquisition mode is entered, a current controlled oscillator is momentarily stopped and then restarted after a variable delay pause to achieve proper phase alignment of the oscillator with an incoming sinusoidal preamble. The variable delay pause is configured as a single fixed delay element and a plurality of variable delay elements adapted to the different frequencies associated with a plurality of recording zones.
However, the selection of ideal delay element values for the clock generating oscillator is not easy, and has heretofore not been optimized to take into account chip to chip variations in logic circuit delays associated with the oscillator starting process. Such variations may result from differences in IC processing during manufacture, chip aging, and changes in environmental conditions occurring during system operation, for example.
Accordingly, it would be desirable to provide a method and apparatus for optimizing the starting phase associated with a timing recovery process in a sampled data detection system. The system should be capable of optimizing the starting phase for timing acquisition in a plurality of different recording zones in a disk drive employing zoned data recording, and should be capable of functioning in a mode that is transparent to the user.